Reduced crosstalk sensor and method of formation

ABSTRACT

Isolation methods and devices for isolating regions of a semiconductor device are disclosed. The isolation methods and structures include forming an isolating trench among pixels or other active areas of a semiconductor device. The trench extends through the substrate to the base layer, wherein a liner may be deposited on the side walls of the trench. A conductive material is deposited into the trench to block electrons from passing through.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor devices, andmore particularly, to trench isolation technology for use insemiconductor devices, including CMOS image sensors.

BACKGROUND OF THE INVENTION

CMOS imagers are increasingly being used as low cost imaging devicesover charge coupled devices (CCD). A CMOS image sensor circuit includesa focal plane array of pixel cells, each one of the cells including aphoto-conversion device for generating and accumulating charge inresponse to light incident on the pixel cell. Each pixel cell alsoincludes devices, e.g., transistors, for transferring charge from thephoto-conversion device to readout circuitry for readout.

FIGS. 1A-1B depict two adjacent conventional CMOS pixel cells 100a, 100bof an array 199. FIG. 1A is a top plan view of the pixel cells and FIG.1B is a cross-sectional view of the pixel cells of FIG. 1A along line1B-1B′. Pixel cells 100a, 100b are formed at a surface of a substrate101. Substrate 101 is a p-type substrate overlying a heavily dopedp-type substrate base 102. Each pixel cell 100a, 100b includes aphoto-conversion device, which is depicted as a pinned photodiode 110a,110b. The pinned photodiodes 110a, 110b respectively include a dopedp-type surface layer 111a, 111b overlying a doped n-type region 112a,112b. The n-type regions serve to accumulate charge carriers, e.g.,electrons, that are generated by photons of light incident on pinnedphotodiodes 110a, 110b and absorbed within substrate 101.

There are sensing nodes, which are depicted as floating diffusion nodes116a, 116b on opposite sides of a respective transfer gate 115a, 115b topinned photodiode 110. Floating diffusion nodes 116a, 116b are dopedn-type regions and receive charge transferred from the pinnedphotodiodes 110a, 110b by the respective transfer gates 115a, 115b.

While not shown in FIGS. 1A-1B, each pixel cell 100a, 100b also includesa respective reset transistor for resetting their floating diffusionregions 116a, 116b to a predetermined voltage before sensing a signal;and a row select transistor for outputting a signal from a sourcefollower transistor to an output terminal in response to an addresssignal. CMOS image sensors of the type discussed above are generallyknown as discussed, for example, in Nixon et al., 256×256 CMOS ActivePixel Sensor Camera-on-a-Chip, IEEE Journal of Solid-State Circuits,Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., CMOS Active PixelImage Sensors, IEEE Transactions on Electron Devices, Vol. 41(3), pp.452-453 (1994). U.S. Pat. Nos. 6,177,333 and 6,204,524 also describeoperation of conventional CMOS image sensors, the contents of which areincorporated by reference herein.

Adjacent pixel cells 100a, 100b, and/or other pixel cells (not shown) ofarray 199, can interfere with each another causing crosstalk, whichresults in poor image quality. Crosstalk can be either optical orelectrical. Isolation techniques have been used to prevent crosstalkbetween pixel cells. This disclosure concerns electrical isolationtechniques to prevent crosstalk. Electrical isolation is complex anddepends on a number of factors including photon absorption in thesubstrate 101, photon wavelength, characteristics of the pinnedphotodiodes 110a, 110b the life-time of minority carriers, andgeneration and recombination centers in the substrate 101, among others.

Shallow trench isolation (STI) is one electrical isolation technique,which has been used to isolate pixels cells, as well as devices orcircuitry, from one other. In general, for STI, a trench 120a, 120b isetched into the substrate 101 and filled with a dielectric to provide aphysical and electrical barrier between adjacent pixels (100a, 110b),devices, or circuitry. The depth of an STI region is generally fromabout 2000 Angstroms (Å) to about 2500 Å.

One drawback associated with STI is crosstalk from a photon that isabsorbed deep within the substrate 101 of pinned photodiodes 110a, 110b.Table 1 shows the absorption depth for photons of different wavelengthsin a silicon substrate.

TABLE 1 Wavelength (Nanometers) Absorption Depth (Microns) 400 0.19 4501.0 500 2.3 550 3.3 600 5.0 650 7.6 700 8.5 750 16 800 23 850 46 900 62950 150 1000 470 1050 1500 1100 7600

Longer wavelength photons are absorbed deep within the substrate 101.Therefore, pinned photodiodes 110a, 110b must have a deeper p-n junctiondepth to capture the long wavelength photons. In the near-infrared andinfrared regions of the spectrum, the absorption depths are high andphotons travel far into the substrate 101 before being absorbed andgenerate charge carriers. Therefore, electrons generated by such photonsmust travel long distances before reaching the floating diffusionregion. Accordingly, there is a greater chance that such electrons willtravel to other pixel cells, causing crosstalk between adjacent pixels.

Accordingly, it is desirable to provide an improved isolation techniquethat prevents crosstalk from one pixel cell to another, and particularlyfrom a pixel cell that absorbs photons having long wavelengths.

BRIEF SUMMARY OF THE INVENTION

The invention provided a deep trench isolation structure and method forreducing crosstalk among semiconductor circuits, and particularly amongadjacent photodiodes formed in pixel circuits. Under a preferredembodiment, a trench is etched into a substrate adjacent to a photodioderegion, wherein the trench extends to an epitaxial layer below thesubstrate. Once the trench is formed, a thin oxide layer is formedinside the trench, or alternately, a layer of dielectric material may bedirectly deposited over the trench. Subsequently, a polysilicondeposition is used to fill the trench.

The foregoing and other advantages and features of the invention willbecome more apparent from the detailed description of exemplaryembodiments provided below with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top plan view of two pixels of a CMOS pixel cell;

FIG. 1B is a cross sectional view of the pixel cell of FIG. 1A;

FIG. 2 is a cross sectional view of a trench according to a firstexemplary embodiment of the invention;

FIG. 3A is a cross sectional view of the pixel cells of FIG. 2A at anintermediate stage of processing;

FIG. 3B is a cross sectional view of the pixel cells of FIG. 2A at anintermediate stage of processing;

FIG. 3C is a cross sectional view of the pixel cells of FIG. 2A at anintermediate stage of processing;

FIG. 4 is a cross sectional view of a trench according to a secondexemplary embodiment of the invention;

FIG. 5 is a cross sectional view of a trench according to a thirdexemplary embodiment of the invention;

FIG. 6 is a cross sectional view of a trench according to a fourthexemplary embodiment of the invention;

FIG. 7 illustrates a trench of the present invention surrounding redpixels of a Bayer pattern; and

FIG. 8 is a schematic diagram of a processor system incorporating anexemplary embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way, of illustration of specific embodiments in which the inventionmay be practiced. These embodiments are described in sufficient detailto enable those skilled in the art to practice the invention, and it isto be understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

The terms “wafer” and “substrate” are to be understood as includingsilicon, silicon-on-insulator (SOI), or silicon-on-sapphire (SOS)technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processsteps may have been utilized to form regions or junctions in the basesemiconductor structure or foundation. In addition, the semiconductorneed not be silicon-based, but could be based on silicon-germanium,germanium, or gallium-arsenide.

The term “pixel” refers to a picture element unit cell having an activearea and containing a photo-conversion device and other devices, e.g.,transistors, for converting electromagnetic radiation to an electricalsignal. For purposes of illustration, a representative pixel cells areillustrated in the Figure s and description herein, and typicallyfabrication of all pixels in an image sensor will proceed simultaneouslyin a similar fashion.

For simplicity, exemplary embodiments described herein are explainedwith reference to a CMOS image sensor. However, it should be noted thatthe invention is not limited to CMOS image sensors and may be used inany suitable device, for example, a charge coupled device (CCD) imagesensor.

Shallow trench isolation regions for CMOS image sensors generally have adepth of less than about 3000 Angstroms (Å) and are generally aroundabout 2000 Å to about 2500 Å. Typically, STI regions are filled with aconventional insulator, such as oxides or high density plasma (HDP)oxides. However, it is difficult to fill trenches having a depth greaterthan 2500 Å with conventional insulators due to the limited spacingwithin the trench, for example, undesirable voids or air gaps are formedwhen oxides are used to fill trenches having a depth greater than about2500 Å. The width (W) may vary, but is preferably shorter than the depth(D) of the trench.

In accordance with an exemplary embodiment of the invention shown inFIG. 2, a trench 202 is preferably filled with conductive materialscontaining silicon, preferably polysilicon or silicon-germanium.Conductive materials containing silicon may be easily deposited intotrenches of various depths, unlike conventional insulation materials,e.g., silicon dioxide, silicon nitride, NO, ON, HDP, and ONO, which aredifficult to fill in deep trenches. Thus, using a conductive materialcontaining silicon, or a combination of such conductive materialscontaining silicon, to fill the trench 202 allows easy formation of atrench, particularly, a deep trench having a depth (D) greater thanabout 2000 Å, and preferably about 4000 to about 5000 Å. In a preferredembodiment, the trench 202 should extend to the epi layer 201 as shownin FIG. 2

Generally, the deeper the trench 202 the better the isolation. Withrespect to CMOS image sensors in particular, the deeper the trench 202the higher the electron storage capacitance of the CMOS image sensor. Atrench according to the invention is deeper than a shallow trench, andaccordingly has longer sidewalls than a shallow trench. Therefore, thelonger sidewalls allow for a larger electrical connection region 323along the sidewalls of the trench 202 such that electron storagecapacitance, e.g., hole accumulation, in the electrical connectionregion 323 is increased in accordance with the invention.

The use of a trench in accordance with the invention provides improvedisolation between pixels. The deeper trench better inhibits electronsfrom diffusing under the isolation trench to an adjacent pixel therebypreventing crosstalk between neighboring pixels. Also the deeper trenchallows for tighter isolation design rules. Deeper trenches may also benarrower than shallow trenches, while still providing effectiveisolation between neighboring regions. Accordingly, the source/drainregions of one pixel may be brought closer to the active layer of anadjacent pixel, by narrowing the width of the deep trench.

The fabrication of an exemplary trench 202 is described below withreference to FIGS. 3A-3C. No particular order is required for any of thesteps described herein, except for those logically requiring the resultsof prior actions. Accordingly, while the steps below are described asbeing performed in a general order, the order is exemplary only and maybe altered.

As shown in FIG. 3A, a trench 202 is etched into substrate 200, which isadjacent to photodiode region 203. The trench 202 preferably extendsnear, or directly above base layer 201. An anisotropic etch is performedinto the silicon substrate 200 to create a deep trench 202. A resist andmask are applied, and photolithographic techniques are used to definethe area to be etched-out of substrate 200. A directional etchingprocess, such as Reactive Ion Etching (RIE), or etching with apreferential anisotropic etchant is used to etch into a doped activelayer to form the trench 202. The resist and mask are removed leaving astructure that appears as shown in FIG. 3A.

Referring now to FIG. 3B, an oxide, i.e., silicon oxide, silicon dioxideor other dielectric liner 204, is grown or deposited on sidewalls 210and bottom 220 of trench 202. The liner may be formed by knowntechniques and may be a high density plasma (HDP) oxide, a spin ondielectric (SOD), e.g., silicon oxide, or other suitable material. Liner204 can be substantially conformal such that the thickness of the liner204 is substantially the same along the sidewalls 210 and at the bottom220 of the trench 202. In general, the thickness of the dielectric liner204 along the sidewalls 210 should be at least about 100 Angstroms.Alternatively, a direct deposit of an insulator could be performed.

Furthermore, part of the trench may be filled with disposable, dopedoxide material after the trench etch to create a film over the trench.The disposable oxide film may be boron-doped BSG, or phosphor-doped PSG,or other suitable material. After the film is deposited in the trench, aHF dip will remove part of the film from the top of the trench, leavingfilm only along the sidewalls and bottom of the trench. A short annealprocess then follows to out-diffuse dopants from the film to thesidewalls of the trench. In this manner, the boron-doped BSG acts as asolid-source diffusion source for boron.

In the case of a PNP photodiode having a BSG film, a high concentrationboron doped region will be formed near the sidewall and the bottom ofthe trench. This high-doped region will serve to connect the top surfacep-layer 203 to the bottom p-substrate epi layer 201 in a pinnedphotodiode structure. Also, high conical sidewalls without the use ofhigh dose implants can create a good interface without defects forreduced dark current.

Referring now to FIG. 3C, a highly doped (in-situ doped) n-type orp-type conductive material containing silicon 205 is deposited to fillthe trench 202. Suitable conductive materials containing silicon includepolysilicon and silicon-germanium. Alternatively, the trench 202 may befilled with an undoped conductive material containing silicon, which canremain free of dopants or be subsequently implanted with dopants. If thetrench is filled with undoped polysilicon that is to be doped, a maskedion implant may be performed to dope the conductive material containingsilicon. For example, in the case of a p-type active layer, with p-typewells, p-type ions such as boron (B) can be implanted into theconductive material 205 containing silicon using a photoresist mask.

Depending on the placement of the epi layer 201, the depth of the trenchcan be tailored to extend to the surface of epi layer 201. For example,if the starting epi thickness is 4 μm deep, a trench having a depth of 3μm would help to connect the buried p or n epi layer 201 to the uppersurface p or n layer 203 after it diffuses out 1.5 μm towards thesurface during the processing steps described above. A much deepertrench (e.g., 8 μm) may be used for such applications as infra-red, ornear infra-red sensors.

FIG. 4 illustrates yet another embodiment of the present invention,according to which trench 302 is lined with an oxide or dielectric liner304 only on the sidewalls of the trench, and not on its bottom. In thismanner, the material filling the trench 302, for example, highly dopedpolysilicon, directly contacts the epi layer 201 located beneath thetrench, providing a hookup area to the substrate 200. In addition, thetwo sidewall STI layers isolate adjacent pixels and provide betterscaling.

As in the previously described embodiment, the trench 302 is etched intosubstrate 200, which is adjacent to photodiode region 203. The trench202 preferably extends near, or directly above base layer 201. Ananisotropic etch is performed into the silicon substrate 200 to create adeep trench. A resist and mask are applied, and photolithographictechniques Are used to define the area to be etched-out of substrate200. A directional etching process, such as Reactive Ion Etching (RIE),or etching with a preferential anisotropic etchant is used to etch intoa doped active layer to form the trench 302.

An oxide, such as silicon oxide, silicon dioxide or other dielectricliner 304 is grown or deposited on sidewalls 310 but not on bottom 320of trench 302, as also shown in FIG. 4. The formation of the dielectricliner 304 only on sidewalls 310 may be accomplished, for example, bymasking the bottom 320 of the trench 302 and then forming the dielectricliner 304 on the sidewalls 310. Alternatively, the dielectric liner 304may be first formed within the trench 302, on both the sidewalls 310 andthe bottom 320, and then removed from the bottom 320. An etchingprocess, such as an HF dip for example, may be conducted to remove partof the film from the bottom of the trench, leaving dielectric film onlyalong the sidewalls of the trench. Liner 304 may be formed by knowntechniques and may be a high density plasma (HDP) oxide, a spin ondielectric (SOD), e.g., silicon oxide, or other suitable material. Ingeneral, the thickness of the dielectric liner 304 along the sidewalls310 should be at least about 100 Angstroms.

A highly doped (in-situ doped) n-type or p-type conductive materialcontaining silicon 305 is next deposited to fill the trench 302.Suitable conductive materials containing silicon include polysilicon andsilicon-germanium. Alternatively, the trench 302 may be filled with anundoped conductive material containing silicon, which can remain free ofdopants or be subsequently implanted with dopants. If the trench isfilled with undoped polysilicon that is to be doped, a masked ionimplant may be performed to dope the conductive material containingsilicon. For example, in the case of a p-type active layer, with p-typewells, p-type ions such as boron (B) can be implanted into theconductive material 305 containing silicon using a photoresist mask.

FIG. 5 illustrates yet another embodiment of the present invention,according to which trench 402 incorporates a plurality of dielectricfilms, at least two of each having different refractive indices. Forexample, FIG. 5 depicts trench 402 containing three materials 410, 420and 430 having different refractive indices. Based on the refractiveindices, the layering structure of materials 410, 420 and 430 isconfigured so that photons entering the trench 402 from adjacentcircuitry will be reflected away from the photodiode region 203.Illustratively, material 410 has a greater refractive index that that ofmaterial 420, which in turn has a greater refractive index than that ofmaterial 430. For exemplary purposes only, the materials havingdifferent refractive indices may comprise any dielectric material, suchas undoped polysilicon, silicon dioxide, aluminum dioxide,spin-on-dielectric (SOD), silicon nitride, or any combination of thesedielectric materials.

A combination of PE-oxide (PECVD oxide) with a refractive index of 1.46and FSG-oxide (fluorinated silica glass oxide) with a refractive indexof 1.435, as well as PE-oxide and FSG-oxide multiple layers, may be alsoused as combinations of materials with different refractive indices tofill in trench 402. The PE-oxide/FSG-oxide combination for improvingoptical crosstalk above the silicon active area of a CMOS image sensoris disclosed, for example, by Hsu et al. in Light Guide for PixelCrosstalk Improvement, Deep Sub-micron CMOS Image Sensor, IEEE Vol. 25,No. 1 (January 2004), the disclosure of which is incorporated byreference herein. By engineering the refractive index between twodielectric materials, for example, the total internal reflection (TIR)is minimized so that the photons that would otherwise get lost areconfined and they bounce off an interface that has refractive indexdifference between the two materials. This, in turn, allows an increasein the quantum efficiency of the array.

Reference is now made to FIG. 6 which illustrates yet another embodimentof the present invention. According to this embodiment, a contact 500 isdropped to the conductive material 205 of trench 502 so that any trappedcharge into the conductive material 205 may be efficiently removed. Thetrench 502 is similar to the trench 202 of FIGS. 3A-3B and is formed bya process similar to that for the formation of the trench 202. Thedifference between the trenches 502 and 202 is that the trench 502 hascontact 500 to the conductive material 205 inside of the trench 502.

Providing contact 500 may be accomplished by strapping the conductivematerial 205 (for example, highly doped polysilicon or undopedconductive material containing silicon) in the array together anddropping a contact in the edge of the array. In this manner, byproviding a contact to the conductive material 205 inside of the trench502, it is possible to bias the conductive material (for examplepolysilicon) negative or positive. Depending on the pinned photodiodestructure and the doping type of the polysilicon, this bias can beadjusted to create an accumulation region around the sidewalls of theSTI. By doing so, it is possible to reduce or eliminate the need fordoping the sidewall region. For example, in a PNP pinned photodiode, thesidewall has to be p-type to hookup to the substrate. If the conductivematerial 205 inside of the trench 502 is n+ polysilicon, this materialcan be biased negatively to create a hole-rich accumulation region onthe sidewalls 210 of the trench 502. Alternatively, if the conductivematerial 205 inside of the trench 502 is p+ polysilicon, then the p+polysilicon would be biased positively. The bias may be in the range ofabout 100 to 500 mV in absolute value. For a NPN pinned photodiode, thebias conditions would be reversed to create an electron-richaccumulation region on the sidewalls 210 of the trench 502.

FIG. 7 illustrate an exemplary application of the deep trench isolationstructures of the present invention to a color filter array 700 forcapturing images in a digital camera, for example. The color filterarray 700 comprises a plurality of deep trench isolation structures,such as the deep trench isolation structures 202 of FIGS. 3A-3C, forexample, provided around the perimeter of predefined pixels 701 coveredby corresponding color filters. For exemplary purposes only, the colorfilter array 700 of the present invention comprises deep trenchisolation structures 202 surrounding red pixels 701 of a color filterarray Bayer pattern. However, the deep trench isolation structures ofthe present invention may be used for isolating pixel cells of any knowncolor filter array, and thus the invention is not limited to a Bayercolor filter array.

As known in the art, a Bayer pattern comprises pixels which arerepresented by squares in the grid of FIG. 7. Each pixel includes anelectronic sensor which measures the light falling on it. Pixels 701have a red filter to measure red light and are represented by an R inthe pattern. Those pixels which have a green filter measure green lightand are represented by a G in the pattern, and those pixels which have ablue filter measure blue light and are represented by a B in thepattern. The Bayer pattern is replicated throughout the entire colorfilter array in both the horizontal and vertical directions. Byproviding deep trenches around the red pixels of a color filter array,such as the Bayer color filter array of FIG. 7, crosstalk between thered pixels (which have a deeper photon absorption than the green andblue pixels) is decreased and the image quality is accordinglyincreased.

Although the deep trench isolation structures have been illustrated inFIG. 7 as completely surrounding the red pixels 701 of a Bayer colorfilter array, it must be understood that this embodiment is onlyexemplary. As such, the present invention also contemplates theformation of deep trench isolation structures, such as the deep trenchisolation structures 202, 302, 402, 502 of the present invention, onlypartially surrounding red pixels of a color filter array, such as thered pixels 701 of the Bayer pattern of FIG. 7. In addition, the deeptrench isolation structures of the present invention may be formedsurrounding totally or partially other pixels of a color filter array,for example the green pixels, or a combination of the red, green andblue pixels of a color array, as desired.

A processor based system 600, which includes a CMOS image sensor 642according to the invention is illustrated in FIG. 8. Processor basedsystem 600 is exemplary of a system having digital circuits, which couldinclude an image sensor. Without being limiting, such a system couldinclude a computer system, camera system, scanner, machine vision,vehicle navigation, video phone, surveillance system, auto focus system,star tracker system, motion detection system, image stabilization systemand data compression system for high-definition television, all of whichcan utilize the present invention.

Processor based system 600, such as a computer system, for examplegenerally comprises a central processing unit (CPU) 644, for example, amicroprocessor, which communicates with an input/output (I/O) device 646over a bus 652. The CMOS image sensor 642 also includes an IC with asingle or multiple isolation trench structures such as the deep trenchisolation structures 202, 302, 402, 502 of the present invention. TheCMOS image sensor 642 also communicates with components of the system600 over bus 652. The computer system 600 also includes random accessmemory (RAM) 648, and, in the case of a computer system may includeperipheral devices such as a flash memory card 654, or a compact disk(CD) ROM drive 656, which also communicate with CPU 644 over the bus652. It may also be desirable to integrate the processor 654, CMOS imagesensor 642 and memory 648 on a single IC chip.

While the above embodiments are described in connection with theformation of PNP-type photodiodes the invention is not limited to theseembodiments. The invention also has applicability to other types ofphotodiodes and to photodiodes formed from npn regions in a substrate.If an NPN-type photodiode is formed the dopant and conductivity types ofall structures would change accordingly.

The above description and drawings are only to be consideredillustrative of exemplary embodiments, which achieve the features andadvantages of the invention. Modification and substitutions to specificprocess conditions and structures can be made without departing from thespirit and scope of the invention. While the above embodiments aredescribed in connection with the formation of PNP-type photodiodes theinvention is not limited to these embodiments. Accordingly, theinvention is not to be considered as being limited by the foregoingdescription and drawings, but is only limited by the scope of theappended claims.

The invention claimed is:
 1. An image sensor comprising: a substrateformed over a base layer; a plurality of pixel cells formed within saidsubstrate, each pixel cell comprising a photo-conversion device having acharge collection region of a second conductivity type for accumulatingphoto-generated charge formed in said substrate below a first layer of afirst conductivity type; and a plurality of trenches, each trench beingprovided along a perimeter of a respective pixel cell, each trenchextending at least to a surface of the base layer and below a lowerlevel of said photo-conversion device, each trench having sidewalls, andbeing at least partially filled with a conductive material that inhibitselectrons from passing through said trench, wherein each of saidplurality of trenches prevents diffusion of photo-generated chargegenerated by said photo-conversion device in one pixel cell to anadjacent pixel cell, and wherein the conductive material is sufficientlybiased to form one of a hole rich or electron rich accumulation layeralong the sidewalls of the trench.
 2. The sensor of claim 1, furthercomprising a dielectric material formed along at least a portion of saidsidewalls.
 3. The sensor of claim 2, wherein the dielectric material isan oxide.
 4. The sensor of claim 2, wherein the dielectric material isformed on the sidewalls of the trench but not on a bottom of the trench.5. The sensor of claim 2, wherein the dielectric material comprises atleast two materials having different indices of refraction.
 6. Thesensor of claim 2, wherein said dielectric material is substantiallyconformal such that thickness of said dielectric material issubstantially same along said sidewalls and a bottom of said trench. 7.The sensor of claim 6, wherein thickness of said dielectric materialalong said sidewalls is greater than about 100 Angstroms.
 8. The sensorof claim 1, wherein said material is a conductive material.
 9. Thesensor of claim 8 1, wherein said conductive material comprises one ofdoped polysilicon, undoped polysilicon and boron-doped carbon.
 10. Thesensor of claim 1, wherein said trench has a depth greater than about2000 Angstroms.
 11. The sensor of claim 10, wherein said trench has adepth in the range of about 4000 to about 5000 Angstroms.
 12. The sensorof claim 1, wherein the sensor comprises a CMOS image sensor.
 13. Thesensor of claim 1, wherein the sensor comprises a CCD image sensor. 14.The sensor of claim 1, wherein the pixel cells are red pixel cells of aBayer pattern.
 15. The sensor of claim 1, further comprising a contactadjacent at least one of the plurality of trenches, for biasing theconductive material within the trench positive or negative.
 16. Thesensor of claim 1, wherein the base layer is an epitaxial layer.
 17. Astructure for isolating an active area on a semiconductor device, saidstructure comprising: a photo-conversion device comprising a dopedcharge collection region of a second conductivity type for accumulatingcharge formed in said active area below a first region of a firstconductivity type; a trench formed in a substrate along at least aportion of a periphery of said active area in said semiconductor device,wherein said trench has sidewalls and a bottom, and wherein said bottomof said trench extends at least only to a surface of a base layer belowsaid substrate which is below a lower level of said photo-conversiondevice, and wherein said trench has sidewalls; a dielectric liner formedalong said sidewalls; and a conductive material formed over saiddielectric liner that at least partially fills said trench and inhibitselectrons from passing through said trench, wherein said trench preventsdiffusion of electrons from said doped charge collection region into aregion outside said active area, and wherein the conductive material issufficiently biased to form one of a hole rich or electron richaccumulation layer along the sidewalls of the trench.
 18. The structureof claim 17, wherein the dielectric liner comprises an oxide material.19. The structure of claim 17, wherein the dielectric liner is one ofhigh-density plasma oxide and spin-on dielectric oxide.
 20. Thestructure of claim 17, wherein the dielectric liner is formed of amaterial selected from the group consisting of silicon dioxide, aluminumoxide, undoped polysilicon, silicon nitride, PE-oxide and FSG-oxide. 21.The structure of claim 17, wherein the dielectric liner is formed of atleast two materials having different indices of refraction.
 22. Thestructure of claim 17, wherein the dielectric liner is formed ofPE-oxide and FSG-oxide.
 23. The structure of claim 17, wherein thematerial is a conductive material.
 24. The structure of claim 23 17,wherein the conductive material comprises one of doped polysilicon,undoped polysilicon and boron-doped carbon.
 25. The structure of claim17, wherein the trench has a depth greater than about 2000 Angstroms.26. The structure of claim 25, wherein the trench has a depth in therange of about 4000 to about 5000 Angstroms.
 27. The structure of claim17, wherein the semiconductor device comprises one of a CMOS imagesensor or a CCD image sensor.
 28. The structure of claim 17, furthercomprising a contact adjacent the trench, for biasing the materialwithin the trench positive or negative.
 29. A processing system, saidprocessing system comprising: a processor; a semiconductor device; atrench formed in a substrate along at least a portion of a periphery ofsaid active area in said semiconductor device, the active area having aphoto-conversion device comprising a charge collection region of n-typeconductivity for accumulating charge and located below a p-type regionof said active area, wherein said trench extends at least only to asurface of a base layer below said substrate and to a level below alower level of said photo-conversion device, and wherein said trench hassidewalls and inhibits diffusion of charge outside said active area; adielectric liner formed along said sidewalls; and a material formed oversaid insulating liner that at least partially fills said trench, thematerial being sufficiently biased to form one of a hole rich orelectron rich accumulation layer along the sidewalls of the trench. 30.The processing system of claim 29, wherein the dielectric liner is anoxide material.
 31. The processing system of claim 29, wherein thedielectric liner is one of high-density plasma oxide and spin-ondielectric oxide.
 32. The processing system of claim 29, wherein theconductive material comprises one of doped polysilicon, undopedpolysilicon and boron-doped carbon.
 33. The processing system of claim29, wherein the trench has a depth greater than about 2000 Angstroms.34. The processing system of claim 33, wherein the trench has a depth inthe range of about 4000 to about 5000 Angstroms.
 35. The processingsystem of claim 29, wherein the semiconductor device comprises a CMOSimage sensor.
 36. The processing system of claim 29, wherein thesemiconductor device comprises a CCD image sensor.
 37. The processingsystem of claim 29, wherein the dielectric liner comprises at least twomaterials having different indices of refraction.
 38. The processingsystem of claim 29, wherein the dielectric liner comprises PE-oxide andFSG-oxide.
 39. The processing system of claim 29, wherein the dielectricliner is provided along the sidewalls of the trench but not on a bottomof the trench.
 40. An image sensor comprising: a pixel array, the pixelarray including a plurality of pixels arranged in columns and rows, eachpixel comprising a respective photodiode disposed in a semiconductorsubstrate and having an n-type charge collection region for accumulatingcharge carriers generated by photons incident on the photodiode; and atrench disposed in the semiconductor substrate and extending to asurface of a p-type underlying layer below a lower level of at least onephotodiode, the trench having sidewalls and being at least partiallyfilled with at least one material having a refractive index that isdifferent from a refractive index of an adjacent material to providephoton isolation using differences in refractive indices, wherein the atleast one material is sufficiently biased to form one of a hole rich orelectron rich accumulation layer along the sidewalls of the trench. 41.The image sensor of claim 40, wherein each said trench is filled withtwo materials.
 42. The image sensor of claim 41, wherein said twomaterials have different indices of refraction.
 43. The image sensor ofclaim 41, wherein a first of said two materials is a liner for liningthe sidewalls.
 44. The image sensor of claim 41, wherein the first ofsaid two materials is the adjacent material.
 45. The image sensor ofclaim 40, wherein the photodiode comprises a pinning layer.
 46. An imagesensor comprising: a pixel array, the pixel array comprising a pluralityof pixels arranged in columns and rows, each pixel comprising arespective photodiode disposed in a semiconductor substrate and havingan n-type charge collection region for accumulating charge carriersgenerated by photons incident on the photodiode; and at least one trenchdisposed in the semiconductor substrate, having sidewalls, extending toa surface of a p-type underlying layer below a lower level of thephotodiode and being filled with a material for providing photonisolation between pixels using differences in refractive indices,wherein the material is sufficiently biased to form one of a hole richor electron rich accumulation layer along the sidewalls of the trench.47. The image sensor of claim 46, wherein the material comprises twodifferent materials.
 48. The image sensor of claim 47, wherein the twomaterials have different indices of refraction.
 49. The imager sensor ofclaim 47, wherein the adjacent material is disposed to line thesidewalls.
 50. The image sensor of claim 47, wherein the photodiodecomprises a pinning layer.
 51. A processing system comprising: aprocessor; a random access memory; a flash memory; a communication pathbetween at least the processor and the random access memory and flashmemory; and an image sensor for receiving an image, generating anelectrical representation of the image, and providing the electricalrepresentation of the image to the communication path, the image sensorcomprising: a pixel array, the pixel array comprising a plurality ofpixels arranged in columns and rows, each pixel comprising a respectivephotodiode disposed in a semiconductor substrate and having an n-typecharge collection region for accumulating charge carriers generated byphotons incident on the photodiode; and a trench disposed in thesemiconductor substrate and extending to a surface of a p-typeunderlying layer below a lower level of at least one photodiode, thetrench having sidewalls and being at least partially filled with atleast one material having a refractive index that is different from arefractive index of an adjacent material to provide photon isolationusing differences in refractive indices, wherein the at least onematerial is sufficiently biased to form one of a hole rich or electronrich accumulation layer along the sidewalls of the trench.
 52. Theprocessing system of claim 51, wherein said processing system is a partof a camera.
 53. The processing system of claim 51, wherein saidprocessing system is a part of a cellular telephone.
 54. An image sensorcomprising: a pixel array, the pixel array including a plurality ofpixels arranged in columns and rows, each pixel comprising a respectivephotodiode disposed in a semiconductor substrate and having an n-typecharge collection region for accumulating charge carriers generated byphotons incident on the photodiode; and a trench disposed in thesemiconductor substrate and extending only to a surface of an underlyinglayer below a lower level of at least one photodiode without contactingthe n-type charge collection region, the trench having sidewalls andbeing at least partially filled with at least one material having arefractive index that is different from a refractive index of anadjacent material to provide photon isolation using differences inrefractive indices, wherein the at least one material is sufficientlybiased to form one of a hole rich or electron rich accumulation layeralong the sidewalls of the trench.
 55. An image sensor comprising: apixel array, the pixel array including a plurality of pixels arranged incolumns and rows, each pixel comprising a respective photodiode disposedin a semiconductor substrate and having an n-type charge collectionregion arranged in a p-type region, the n-type region for accumulatingcharge carriers generated by photons incident on the photodiode; and atrench disposed in the semiconductor substrate and extending throughonly the p-type region to a surface of an underlying layer below a lowerlevel of at least one photodiode, the trench having sidewalls and beingat least partially filled with at least one material having a refractiveindex that is different from a refractive index of an adjacent materialto provide photon isolation using differences in refractive indices,wherein the at least one material is sufficiently biased to form one ofa hole rich or electron rich accumulation layer along the sidewalls ofthe trench.